Cold cathode electron emission devices are based on the phenomenon of high field emission wherein electrons can be emitted into a vacuum from a room temperature source if the local electric field at the surface in question is high enough. The creation of such high local electric fields does not necessarily require the application of very high voltage, provided the emitting surface has a sufficiently small radius of curvature.
The advent of semiconductor integrated circuit technology made possible the development and mass production of arrays of cold cathode emitters of this type. In the past, cold cathode field emission displays have been based on an array of very small conical emitters (typically made of molybdenum), each of which is connected to a source of negative voltage via a cathode conductor line or column. Another set of conductive lines (called gate lines) is located a short distance above the cathode lines at an angle (usually 90.degree.) to them, intersecting with them at the locations of the conical emitters or microtips, and connected to a source of positive voltage. Both the cathode and the gate line that relate to a particular microtip must be activated before there will be sufficient voltage to cause cold cathode emission.
The electrons that are emitted by the cold cathodes accelerate past openings in the gate lines and strike a phosphor layer panel that is located a short distance from the gate lines. Note that, even though the local electric field in the immediate vicinity of a microtip is in excess of 1 million volts/cm., displays of this type could be operated using externally applied voltages of the order of 100 volts. Although such displays are practical, the requirement of maintaining a 100 volts or more across what might be a hand-held device has led to a search for cold cathode devices capable of operating at voltages an order of magnitude or more less than this.
A recent promising approach to solving this problem has been the development of carbon nanotubes. These microtubules have tips whose effective radius of curvature is only about 100 Angstroms so that local electric fields in excess of 10.sup.6 volts/cm can be generated there with the application of external voltages of between about 10 and 50 volts.
To illustrate the process currently in use in the prior art for the fabrication of a single cold cathode cell based on carbon nanotubes, we refer now to FIG. 1 where we show, in schematic cross-section, the starting point for manufacturing the device. Cathode layer 12 sits atop substrate 11. In an actual display panel, layer 12 would have the form of series of metallic lines generally referred to as cathode columns. At regular intervals along the cathode columns, the cold emitters are to be formed.
Coating layer 12 is catalyst substrate layer 13. It has been found that the catalytic layer from which the nanotubes are grown (see below) is more effective if laid down onto certain substrates. Two examples of a suitable catalyst substrate material are porous silicon and amorphous silicon. With layer 13 in place, dielectric layer 14 is laid down. This layer supports conductive layer 16 which, in a full display, would be used to form gate lines which run orthogonally relative to the cathode lines. Openings 15 in the gate lines 16 are formed at their intersections (overlaps) with the cathode columns. Thus, when sufficient voltage is applied between the gate lines and the cathode columns cold cathode emission is initiated from whatever electron sources are located inside the cavities.
After emerging through the openings 15 in the gate lines, electrons are further accelerated so that they strike a fluorescent screen (not shown) where they emit visible light. Said screen is part of a top assembly which comprises a glass plate coated with a phosphor layer, the space between them being evacuated and then maintained at a vacuum of the order of 10.sup.-7 torr.
In practice, the diameter of the gate opening is made somewhat less than the diameter of the cavity in which the emitter is housed so as to allow more room for the latter. As already noted, said emitter, until recently, has been in the form of a micro-cone. FIG. 2 illustrates the next step in the process used by the prior art when carbon nanotubes are to be used instead. Catalytic layer 21 is laid down by vacuum evaporation, patterned layer 16 acting as a mask for the incoming vapor stream 22.
Layer 21 is then caused to break up into a discontinuous layer of island areas (see later) each of which becomes a micro-catalyst that serves as a nucleation point for the growth of a nanotube. The latter process is achieved through chemical vapor deposition (CVD) from a high carbon density gas such as ethylene or acetylene. The effect of this is illustrated in FIG. 3 which shows layer 31 (originally layer 21 prior to its getting broken up) up from which nanotubes such as 32 have grown. The CVD process is maintained until the tips of these microtubes come level with layer 16, at which point it is terminated.
While the above described process works as described, it can be seen that the geometry of the situation is such that the separation 33 between an outermost nanotube and the inside edge of the gate aperture 35 will be very small and will be independent of the size of said gate aperture. Furthermore, since precise perpendicularity of the nanotubes cannot always be guaranteed, there is a very real danger that the nanotubes may actually touch the gate layer, resulting in a complete short circuit of the emitter. This is the problem that the present invention will deal with.
A routine search of the prior art was done but no references that teach the approach described in the present invention were found. Several references of interest were, however, encountered. In particular, Z. P. Huang et al. (App. Phys. Lett. 73 No. 26, December 1998, pp. 3845-3847) describe the basic process for forming carbon nanotubes while Shoushan Fan et al. (Science 283 January 1999, pp. 512-514) describe the formation of large arrays of nanotubes. They note that these are promising candidates for field emission applications such as flat panel displays, but point out that scaling these devices for use in larger displays continues to be a problem.